The present invention relates to a method for fabricating a memory cell including at least one selection transistor and a storage capacitor having a high-epsilon or ferroelectric dielectric. The selection transistor is disposed in a first plane and the storage capacitor is disposed in a second plane in and, respectively, above a semiconductor body. The first plane is electrically connected to the second plane by a first plug made of silicon, which is adjoined by a second plug made of silicon, which is electrically connected to a storage node electrode of the storage capacitor.
A prior art memory cell is disclosed in German Published, Non-Prosecuted Patent Application DE 195 40 213A1. Additionally, German Patent DE 195 43 539 C1 describes a method for fabricating a memory configuration in which first plugs are introduced into a first insulating layer proposed on a semi-conductor body. Second plugs are then provided above the first plugs in a second insulating layer applied on the first insulating layer.
In the fabrication of such memory cells, the dielectric made of high-epsilon or ferroelectric material, such as, for example, barium strontium titanate (BST) or bismuth barium tantalate (SBT), requires heat treatment with oxygen. During such heat treatment, however, every uncovered silicon layer is oxidized, resulting in the loss of its electrical conductivity. In memory cells, polycrystalline silicon is used in plugs to connect the selection transistor to an electrode of the stacked storage capacitor disposed above it. These plugs are connecting layers that ensure an electrical connection between the storage capacitor and the selection transistor. In order then to prevent the oxidation of the polycrystalline silicon in the plug between selection transistor and storage capacitor during the heat treatment of BST or SBT, the surface of the plug has hitherto usually been coated with a barrier layer in order to prevent oxygen diffusion to the polycrystalline silicon from taking place. However, it is difficult and also costly to find suitable materials for such barrier layers because the layers have to withstand high temperatures in the region of 700xc2x0 C. and 800xc2x0 C. during the heat treatment of BST and SBT.
It is accordingly an object of the invention to provide a method for fabricating a memory cell that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which, without using a barrier layer, the selection transistor can be electrically well-connected to the storage capacitor such that oxidation of silicon cannot occur.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a memory cell, including the steps of forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane, forming an interspace between two adjacent structures of the polycrystalline silicon layer, placing one of the adjacent structures of the polycrystalline silicon layer on a surface of a first silicon plug, forming a cell plate electrode in the interspace, forming a trench in the polycrystalline silicon layer, the trench reaching as far as the surface of the first plug, and filling the trench with an insulating layer, removing the polycrystalline silicon layer, forming a storage capacitor having one of a high-epsilon and ferroelectric dielectric and a storage node electrode, the storage capacitor being disposed in a second plane in and, respectively, above the semiconductor body, and replacing the insulating layer with silicon to form a second silicon plug directly connected to the first plug, the second plug being electrically connected to the storage node electrode, and the first plane being electrically connected to the second plane through the first and second plugs.
The method for fabricating a memory cell according to the invention achieves its objective by virtue of the fact that, before the application of the dielectric and after the formation of a cell plate electrode for the storage capacitor, a surface of the first plug that is uncovered in a window of a polycrystalline silicon layer is covered with an insulating layer as spacer. Then, the dielectric and subsequently storage node electrodes are formed. Finally, the insulating layer is replaced by silicon, which forms the second plug directly connected to the first plug.
The first plug and the second plug are preferably formed from polycrystalline silicon. As an alternative, they may also be formed from amorphous silicon.
In accordance with another mode of the invention, a lateral edge web is formed on a structure of the polycrystalline silicon layer.
In accordance with a further mode of the invention, a cell plate electrode is formed from a conformal layer and a filling.
In accordance with an added mode of the invention, a cell plate electrode is formed from a conformal layer and a filling.
In accordance with an additional mode of the invention, the insulating layer is formed from at least one of the group consisting of silicon oxide, silicon nitride, and silicon oxide-nitride. Preferably, the insulating layer is formed from silicon nitride.
For the method according to the invention, the cell plate electrode of the storage capacitors is produced by an auxiliary structure in the shape of a reticulated pattern. Contact holes for the cell node connection are then etched into the auxiliary structure, which is preferably formed from polycrystalline silicon. The contact holes are subsequently filled with an insulating layer, for example, made of silicon nitride, as a spacer. The fabrication of the storage capacitor then follows, in which an oxidizing heat treatment of BST or SBT at high temperatures can be performed in a straightforward manner because the plug leading away from the selection transistor is still covered with the insulating layer at this time, so that oxidation of the silicon of the plug is reliably avoided. The silicon forming the second plug replaces the xe2x80x9cspacerxe2x80x9d made of the insulating layer only after the heat treatment.
In accordance with yet another mode of the invention, at least one of the cell plate electrode and the storage node electrode is formed by chemical vapor deposition.
In accordance with yet a further mode of the invention, at least one of the cell plate electrode and the storage node electrode is formed by sputtering.
The electrodes themselves can be formed, for example, by chemical vapor deposition (CVD) of ruthenium (Ru) or, alternatively, by sputtering platinum (Pt) and filling the shrink holes with tungsten. Instead of ruthenium, platinum and tungsten, it is also possible to use other materials, such as those specified, in particular, in U.S. Pat. No. 5,554,866 to Nishioka et al.
With the objects of the invention in view, there is also provided a method for fabricating a memory cell, including the steps of forming a memory cell having a semiconductor body with at least one selection transistor disposed in a first plane and a storage capacitor, the storage capacitor having a storage node electrode and one of a high-epsilon and ferroelectric dielectric, the storage capacitor being disposed in a second plane in and, respectively, above the semiconductor body, and electrically connecting the first plane to the second plane with a first silicon plug by adjoining the first plug to a second silicon plug and by electrically connecting the second plug to the storage node electrode, the forming step including the steps of forming a polycrystalline silicon layer on the semiconductor body, the polycrystalline silicon layer having an interspace between two adjacent structures of the polycrystalline silicon layer, one of the adjacent structures of the polycrystalline silicon layer being disposed on a surface of the first plug, forming a cell plate electrode in the interspace forming a trench in the polycrystalline silicon layer, the trench reaching as far as the surface of: the first plug, and filling the trench with an insulating layer, removing the polycrystalline silicon layer, forming the dielectric and the storage node electrode, and replacing the insulating layer with silicon to form the second plug directly connected to the first plug.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a memory cell, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.